Usually, a chip-size semiconductor package includes a Si chip; metal pads formed on the Si chip; a wafer coating formed over the Si chip; conductive wiring patterns formed on the wafer coating; a molding resin formed over the wafer coating; conductive posts formed in the molding resin; and terminals formed on the conductive posts. The conductive wiring patterns are electrically connected to the metal pads through the wafer coating. The terminals are connected to the conductive posts one by one.
According to the conventional chip-size package, a connecting portion (boundary portion) between the conductive post and wiring pattern is extremely narrow and weak. Therefore, the connecting portion may be broken by stress, which is generated when the molding resin is expanded or contracted.
According to another conventional chip-size semiconductor package, the connecting portion is shaped to decrease in area gradually from the conductive post to conductive wiring pattern. However, the area to be in contact with the molding resin is increased, so that the molding resin may be easily removed from the conductive post and conductive wiring pattern. As a result, the connecting portion may be broken later.